The invention relates to the design and layout of integrated circuits and, in particular, to methods and apparatus for constraining global routing of an integrated circuit layout.
In the field of integrated circuit (IC) development, there is an ever-increasing demand for IC layout tools that are faster, more efficient, and more reliable than their predecessors. This is because there is an ever-accelerating focus upon shortening IC development cycles and time to market, reducing IC development and manufacturing costs, and increasing IC product reliability.
As is well known to IC developers, a process known as xe2x80x9cglobal routingxe2x80x9d can be used to route the interconnections (also called xe2x80x9cnetsxe2x80x9d) between terminals on an IC. Global routing uses a divide-and-conquer approach, wherein an IC layout is divided into a rectilinear grid of global routing cells (also called xe2x80x9cartificial regionsxe2x80x9d or xe2x80x9cARsxe2x80x9d), and the router plans global routes for the nets in a rectilinear fashion using the cells. Within the global routing cells, detailed routing of nets is generated based upon the global routes.
Global routers often require successive iterations of the routing process until the layout meets a desired set of design specifications. While global routing achieves high density, it often provides poor controllability. Successive iterations of global routing with small changes to the layout may result in large changes to the routing. This is undesirable, because it can result in a failure to achieve timing convergence of the routing. Because the circuit interconnect contributes significantly to timing delays in the IC circuits, the changes in topology can lead to large changes in the timing delays of circuits. Thus, in order to achieve timing convergence of routing, successive iterations should not cause large changes in the timing delays of circuits.
For the reasons stated above, there is a substantial need in the area of IC layout to provide a global routing system and methods that do not cause large changes in the timing delays of circuits on successive iterations.
In addition, there is a substantial need to provide an IC having a layout that has been generated by a system and methods that do not cause large changes in the timing delays of the IC""s circuits on successive iterations.
Accordingly, in one embodiment of the invention there is provided a method adapted to be used in a data processing system. The method includes defining a set of constraints for global routing of an integrated circuit layout. The set of constraints comprises at least one topological constraint. The method also includes performing global routing in accordance with the set of constraints.
In another embodiment, there is provided a data processing system comprising a processor and a memory. The processor executes a computer program stored in the memory. The computer program includes the operation of accessing from the memory a set of constraints for global routing of an integrated circuit layout. The set of constraints comprises at least one topological constraint. The computer program also includes the operation of performing global routing in accordance with the set of constraints.
In a further embodiment, there is provided an integrated circuit having a layout generated by a process which comprises defining a set of constraints for global routing of the integrated circuit layout. The set of constraints comprises at least one topological constraint. The process further includes performing global routing in accordance with the set of constraints.
Additional embodiments are described and claimed.